Scaling makes digital circuits highly vulnerable to faults, hence, fault detection and correction in digital systems is crucial. This problem becomes more serious when the complexity and frequency of the system on a chip increase in order to achieve higher performance. Addition is one of the fundamental mathematical operators, which is also the basis of many other operations such as subtraction, multiplication, and addressing. Therefore, designing a fault-tolerant adder is a hot topic in VLSI circuits. In such circuits, the important issue of detecting and correcting multiple faults while using few hardware resources is of high interest from the aspect of circuit design optimization. In this paper, a fast adder is used, and the ability to detect and correct multiple errors is supplemented. In the proposed architecture, a self-testing full adder is designed based on multiplexers, and then this full adder is incorporated to design a self-testing multi-bit fast adder. Furthermore, a self-correcting full adder is designed using redundancy, and then this full adder is applied to design a self-correcting multi-bit fast adder. The syntheses and simulations of the proposed adders are performed for 8, 16, 32, and 64 bits. The obtained results show that the proposed adders outperform recent works in terms of the used hardware resources and the multiple faults detection and correction capability.