International Journal of Nonlinear Analysis and Applications
Fast adder with the ability of multiple faults detection and correction
Document Type : Research Paper
Authors
Dept. of Electrical and Computer Engineering, Babol Noshirvani University of Technology, Babol, Iran.
Abstract
Scaling makes digital circuits highly vulnerable to faults, hence, fault detection and correction in digital systems is crucial. This problem becomes more serious when the complexity and frequency of the system on a chip increase in order to achieve higher performance. Addition is one of the fundamental mathematical operators, which is also the basis of many other operations such as subtraction, multiplication, and addressing. Therefore, designing a fault-tolerant adder is a hot topic in VLSI circuits. In such circuits, the important issue of detecting and correcting multiple faults while using few hardware resources is of high interest from the aspect of circuit design optimization. In this paper, a fast adder is used, and the ability to detect and correct multiple errors is supplemented. In the proposed architecture, a self-testing full adder is designed based on multiplexers, and then this full adder is incorporated to design a self-testing multi-bit fast adder. Furthermore, a self-correcting full adder is designed using redundancy, and then this full adder is applied to design a self-correcting multi-bit fast adder. The syntheses and simulations of the proposed adders are performed for 8, 16, 32, and 64 bits. The obtained results show that the proposed adders outperform recent works in terms of the used hardware resources and the multiple faults detection and correction capability.
Keywords
1443-1451.
[2] T. Ban and L. Naviner, Optimized robust digital voter in tmr designs, in Colloque National GdR SoC-SiP, 2011.
[3] S. Habinc, Functional triple modular redundancy (FTMR), Gaisler Research, 2002.
[4] Y. Jiang, A. Al-Sheraidah, Y. Wang, E. Sha and J.-G. Chung, A novel multiplexer-based low-power full adder,
IEEE Transactions on Circuits and Systems II: Express Briefs. 51 (2004) 345-348.
[5] C. Khedhiri, M. Karmani, B. Hamdi and K. L. Man, Concurrent error detection adder based on two paths output
computation, in Parallel and Distributed Processing with Applications Workshops (ISPAW), 2011 Ninth IEEE
International Symposium on, 2 (2011), 27-32.
[6] C. Khedhiri, M. Karmani, B. Hamdi, K. L. Man, Y. Yang and L. Cheng, A self-checking CMOS full adder in
double pass transistor logic, in International Conference on Engineers and Computer Scientst IMECS, 2012.
[7] R. V. Kshirsagar and R. M. Patrikar, Design of a novel fault-tolerant voter circuit for TMR implementation to
improve reliability in digital circuits, Microelectronics Reliability. 49 (2009) 1573-1577.
[8] C. D. Martinez, L. D. Bollepalli and D. H. Hoe, A fault tolerant parallel-prefix adder for VLSI and FPGA design,
in Proceedings of the 2012 44th Southeastern Symposium on System Theory (SSST), 2012, pp. 121-125.
[9] H. Moradian and J. A. Lee, Self-repairing radix-2 signed-digit adder with multiple error detection, correction, and
fault localization, Microelectronics Reliability. 63 (2016) 256-66.
[10] L.B. Moraes and A. L. Zimpeck, Evaluation of variability using Schmitt trigger on full adders layout. Microelectronics Reliability. 1;88 (2018 ) 116-21.
[11] A. Mukherjee and A. S. Dhar, Double-fault tolerant architecture design for digital adder, in Students’ Technology
Symposium (TechSym), 2014 IEEE, 2014, pp. 154-158.
[12] A. Mukherjee and A. S. Dhar, Design of a Self-Reconfigurable Adder for Fault-Tolerant VLSI Architecture, in
Electronic System Design (ISED), 2012 International Symposium on, 2012, pp. 92-96.
[13] A. Namazi, Y. Sedaghat, S. G. Miremadi and A. Ejlali, A low-cost fault-tolerant technique for Carry Look-Ahead
adder, in 2009 15th IEEE International On-Line Testing Symposium, 2009, pp. 217-222.
[14] R. Rajaei, Highly reliable and low-power magnetic full-adder designs for nanoscale technologies, Microelectronics
Reliability. 73(2017) 129-35.
[15] M. Samie, G. Dragffy, A. M. Tyrrell, T. Pipe and P. Bremner, Novel bio-inspired approach for fault-tolerant VLSI
systems, IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 21(2013) 1878-1891.
[16] R. Shalem, E. John and L. John, A novel low power energy recovery full adder cell, in VLSI, 1999. Proceedings.
Ninth Great Lakes Symposium on, 1999, pp. 380-383.
[17] H. Tavakolaee, Gh. Ardeshir and Y. Baleghi, Fast Mux-based Adder with Low Delay and Optimized PDP, Journal
of AI and Data Mining. 7; 3 (2019) 385-392.[18] M. Valinataj, A novel self-checking carry lookahead adder with multiple error detection/correction, Microprocessors and Microsystems, 38 (2014) 1072-1081.
[19] M. Valinataj , Fault-tolerant carry look-ahead adder architectures robust to multiple simultaneous errors, Microelectronics Reliability. 55 (2015) 2845-57.
)
Volume 12, Special Issue
December 2021Pages 937-950
- Receive Date: 07 January 2021
- Revise Date: 19 May 2021
- Accept Date: 30 June 2021