International Journal of Nonlinear Analysis and Applications
Design of MOESI protocol for multicore processors based on FPGA
Document Type : Research Paper
Authors
1 Al-Farahidi University, Baghdad, Iraq
2 MID, Al-Esraa University College, Baghdad, Iraq
Abstract
Today’s multi-core processors are built by all processor manufacturers for computers, cell phones, and other embedded systems. For all computer engineers, designing and researching the hardware architecture of multicore systems is critical. The type of cache coherence protocol employed on a multi-core computer has a direct impact on execution time, latency, and power consumption. Because it is a good example of a CPU, a 32-bit MIPS processor was chosen. With the addition of our prior work, an advanced special circuit was created using VHDL coding and ISE Xilinx software to implement it. One protocol was utilized in this design, the MOESI (Modify, Owned, Exclusive, Shared, and Invalid) protocol. The result of the test was obtained using a test bench, and they revealed that all of the protocols’ states were operational.
Keywords
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Operating Systems (ASPLOS). ACM, 2000.
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ZigBee, Telkomnika , 18 (1) (2020)282-288.
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of Engineering and Natural Sciences, 7 (2) (2019)10-13.
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processors, in Proceedingsof the ACM/SIGDA international symposium on Field Programmable Gate Arrays,
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in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2019.
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internet of things, International Journal of Engineering & Technology 7, (4) (2018) 2773-2778.
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Research, 2020, ISSN 2090-1232, https://doi.org/10.1016/j.jare.2020.08.015. .
[16] A.J. Obaid , Critical Research on the Novel Progressive, JOKER an Opportunistic Routing Protocol Technology for
Enhancing the Network Performance for Multimedia Communications, 1254 (2021). https://doi.org/10.1007/978-
981-15-7527-3 36.
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in Proceedings of the 22th International Conference on Architectural Support for Programming Languages and
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on Microarchitecture (MICRO). ACM, 2013.
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in 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems
(DFT), Oct 2012.
[23] A. Singh, S. Aga, and S. Narayanasamy, Efficiently Enforcing Strong Memory Ordering in GPUs, in Proceedings
of the 48th International Symposium on Microarchitecture (MICRO). ACM, 2015.
[24] D. J. Sorin, M. D. Hill and D. A. Wood, A Primer on Memory Consistency and Cache Coherence, 1st ed. Morgan
& Claypool Publishers, 2011.
[25] I. Wagner and V. Bertacco, Caspar: Hardware patching for multicore processors, in 2009 Design, Automation
Test in Europe Conference Exhibition, April 2009.[26] A. W. Wilson Jr, Hierarchical Cache/Bus Architecture for Shared Memory Multiprocessors, in Proceedings of the
14th International Symposium on Computer Architecture (ISCA). ACM, 1987.
[27] D. A. Wallach, PHD: A Hierarchical Cache Coherent Protocol, Ph.D. dissertation, Massachusetts Institute of
Technology, 1992.
[28] P. S. a. W. Zhang, WCET Estimation of Multi-Core Processors with the MSI Cache, 2013.
and cloud computing development based on unified citizen identification, Periodicals of Engineering and Natural
Sciences, 7 (4) (2019)1776-1793.[2] J. Alsop, M. D. Sinclair, and S. V. Adve, Spandex: A Flexible Interface for Efficient Heterogeneous Coherence,
in Proceedings of the 45th International Symposium on Computer Architecture (ISCA). IEEE, 2018.
[3] D. Borodin and B. H. H. Juurlink, A low-cost cache coherence verification method for snooping systems, in 2008
11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools, Sep. 2008.
[4] J. F. Cantin, M. H. Lipasti, and J. E. Smith, Dynamic verification of cache coherence protocols, in High Performance Memory Systems. Springer, 2004.
[5] A. DeOrio, A. Bauserman, and V. Bertacco, Post-silicon verification for cache coherence, in 2008 IEEE International Conference on Computer Design, Oct 2008.
[6] R. Fuchsen, How to address certification for multicore based IMA platforms: current status and potential solutions,
Digital Avionics Systems Conference (DASC), 3 (12) (2010).
[7] K. Gharachorloo, M. Sharma, S. Steely and S. Van Doren, Architecture and Design of AlphaServer GS320,
in Proceedings of the 9th International Conference on Architectural Support for Programming Languages and
Operating Systems (ASPLOS). ACM, 2000.
[8] Z.K. Hussein, H.J. Hadi, M.R. Abdul-Mutaleb, Y.S. Mezaal, Low cost smart weather station using Arduino and
ZigBee, Telkomnika , 18 (1) (2020)282-288.
[9] A. Ibrahim, H. Ahmed and F. Jumma, MESI Protocol for Multicore Processors Based on FPGA, in Periodicals
of Engineering and Natural Sciences, 7 (2) (2019)10-13.
[10] A. Kaushik, M. Hassan and H. Patel Designing Predictable Cache Coherence Protocols for Multi-Core Real-Time
Systems, in IEEE Transactions on Computers, 2020.
[11] M. Kinsy, M. Pellauer, and S. Devadas, Heracles: A tool for fast rtlbased design space exploration of multicore
processors, in Proceedingsof the ACM/SIGDA international symposium on Field Programmable Gate Arrays,
ser. FPGA ’13. New York, NY, USA: ACM, 2013.
[12] B. Kumar, A. Kumar, M. Fujita and V. Singh Validating Multi-Processor Cache Coherence Mechanisms under
Diminished Observability, in Proceedings of the 45th International Symposium on Computer Architecture (ISCA).
2019 IEEE 28th Asian Test Symposium (ATS), 2019.
[13] Y. Lyu, X. Qin, M. Chen and P. Mishra Directed Test Generation for Validation of Cache Coherence Protocols,
in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2019.
[14] A.A.H. Mohamad, Y. S. Mezaal and S. F. Abdulkareem, Computerized power transformer monitoring based on
internet of things, International Journal of Engineering & Technology 7, (4) (2018) 2773-2778.
[15] Ch. Meshram, W. Ibrahim, J. Obaid, S. Gajbhiye Meshram, A. Meshram and A. Mohamed Abd El-Latif, Fractional chaotic maps based short signature scheme under human-centered IoT environments, Journal of Advanced
Research, 2020, ISSN 2090-1232, https://doi.org/10.1016/j.jare.2020.08.015. .
[16] A.J. Obaid , Critical Research on the Novel Progressive, JOKER an Opportunistic Routing Protocol Technology for
Enhancing the Network Performance for Multimedia Communications, 1254 (2021). https://doi.org/10.1007/978-
981-15-7527-3 36.
[17] L. E. Olson, M. D. Hill, and D. A. Wood, Crossing Guard: Mediating Host-Accelerator Coherence Interactions,
in Proceedings of the 22th International Conference on Architectural Support for Programming Languages and
Operating Systems (ASPLOS). ACM, 2017.
[18] M. S. Papamarcos and J. H. Patel, A low-overhead coherence solution for multiprocessors with private cache
memories, in Proceedings of the 11th Annual Symposium on Computer Architecture, Ann Arbor, USA, 1984.
[19] F. Pong and M. Dubois, A new approach for the verification of cache coherence protocols, IEEE Trans. Parallel
Distrib. Syst., 6 (8) (1995) 773–787.
[20] F. Pong and M. Dubois, The verification of cache coherence protocols, in Proceedings of the Fifth Annual ACM
Symposium on Parallel Algorithms and Architectures, ser. SPAA ’93. New York, NY, USA: ACM, 1993.
[21] J. Power, A. Basu, J. Gu, S. Puthoor, B. M. Beckmann, M. D. Hill, S. K. Reinhardt, and D. A. Wood, Heterogeneous System Coherence for Integrated CPU-GPU Systems, in Proceedings of the 46th International Symposium
on Microarchitecture (MICRO). ACM, 2013.
[22] R. Rodrigues, I. Koren, and S. Kundu, A mechanism to verify cache coherence transactions in multicore systems,
in 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems
(DFT), Oct 2012.
[23] A. Singh, S. Aga, and S. Narayanasamy, Efficiently Enforcing Strong Memory Ordering in GPUs, in Proceedings
of the 48th International Symposium on Microarchitecture (MICRO). ACM, 2015.
[24] D. J. Sorin, M. D. Hill and D. A. Wood, A Primer on Memory Consistency and Cache Coherence, 1st ed. Morgan
& Claypool Publishers, 2011.
[25] I. Wagner and V. Bertacco, Caspar: Hardware patching for multicore processors, in 2009 Design, Automation
Test in Europe Conference Exhibition, April 2009.[26] A. W. Wilson Jr, Hierarchical Cache/Bus Architecture for Shared Memory Multiprocessors, in Proceedings of the
14th International Symposium on Computer Architecture (ISCA). ACM, 1987.
[27] D. A. Wallach, PHD: A Hierarchical Cache Coherent Protocol, Ph.D. dissertation, Massachusetts Institute of
Technology, 1992.
[28] P. S. a. W. Zhang, WCET Estimation of Multi-Core Processors with the MSI Cache, 2013.
)
Volume 12, Special Issue
December 2021Pages 1229-1242
- Receive Date: 06 June 2021
- Revise Date: 10 July 2021
- Accept Date: 28 September 2021