This paper proposes an area and power efficient technique for the design of an ECG detector. In biomedical applications, like the ECG detector for implantable cardiac pacemaker systems, area and power consumption plays a major role. Thus in this paper, an area-efficient ECG detector with folded pipelined FIR filter is proposed. In conventional wavelet filter bank structure, the decimated wavelet filter bank used makes use of 3 LPFs and 1 HPF of pipelined architecture. This pipelined filter structure requires more hardware. Thus in the proposed architecture folding transformation technique has been applied to the pipelined filter structure in order to reduce the hardware. The decimated wavelet filter bank consisting of the filter structures followed by down samplers is used to denoise the ECG signal. The QRS complex detector consisting of a comparator, counter and a threshold block is used to find the correct location of the QRS complex. In order to further reduce the number of registers that occurs as a result of the folding transformation, folding transformation with register minimization technique is applied to the pipelined filter that results in less hardware utilization. The proposed technique is implemented using Xilinx System Generator. Thus a total area of 22.78% is saved using the proposed method. Considerably a low power of 115mW is also achieved which makes it useful for high-performance medical applications.